A simulated annealing approach for high-level synthesis with reconfigurable functional units

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 1996

Autores

José Carlos Alves (Autor) FEUP; José Silva Matos (Autor) FEUP

Ata de Conferência Internacional

Título: 38TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, PROCEEDINGS, VOLS 1 AND 2

Páginas: 314-317

38th Midwest Symposium on Circuits and Systems

RIO JANEIRO, BRAZIL, AUG 13-16, 1995

Indexação

ISI Web of Knowledge - 0 Citações

Scopus - 4 Citações

Outras Informações

ID Authenticus: P-001-FS3

Abstract (EN): In this paper, we present an application of the simulation annealing optimization algorithm to the problem of high-level synthesis of digital systems, targeted to architectures with run-time reconfigurable functional units. The scheduling, allocation and binding problems are treated simultaneously. Reconfiguration times and execution delays are taken into account, along with pipelined execution and precise clock cycles for consumption of each operand.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4