Abstract (EN):
This paper presents a set of modifications to
common processor on-chip debugging infrastructures
to support the execution of fault injection campaigns.
The proposed solution is applicable to different target
architectures and imposes a very low logic overhead,
providing a flexible and efficient mechanism for
verifying and validating fault tolerant components.
Idioma:
Inglês
Tipo (Avaliação Docente):
Científica
Tipo de Licença: