A framework for fault tolerant real time systems based on reconfigurable FPGAs

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2006-09

Autores

José M. Ferreira (Autor) FEUP; Manuel G. Gericota (Autor) Outra; Luís F. Lemos (Autor) Outra; Gustavo R. Alves (Autor) Outra; Mário M. Barbosa (Autor) Outra

Ata de Conferência Internacional

Título: 2006 IEEE CONFERENCE ON EMERGING TECHNOLOGIES & FACTORY AUTOMATION, VOLS 1 -3

Páginas: 131-138

11th IEEE International Conference on Emerging Technologies and Factory Automation

Prague, CZECH REPUBLIC, SEP 20-22, 2006

Indexação

ISI Web of Science

Scopus

INSPEC

Classificação Científica

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

DOI: 10.1109/ETFA.2006.355409

Abstract (EN): To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 8