A test infrastructure for compilers targeting FPGAs

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2005

Autores

Rodrigues, RMM (Autor) Outra; João M. P. Cardoso (Autor) Outra

Ata de Conferência Internacional

Título: ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005

Páginas: 168-175

International Workshop on Applied Reconfigurable Computing 2005, ARC 2005

Algarve, 22 February 2005 through 23 February 2005

Indexação

Scopus - 3 Citações

Outras Informações

ID Authenticus: P-009-457

Abstract (EN): This paper presents an infrastructure to verify the functionality of the specific architectures generated by a high-level compiler, targeting dynamically reconfigurable hardware. Java, XML, and XSL technologies are used to support the infrastructure. As simulation engine we use Hades, an event driven Java based simulator. It results in a suitable scheme to test the designs generated by the compiler each time a new optimization technique is included or changes in the compiler are performed. We believe this infrastructure will be very important to verify, by functional simulation, further research techniques, as far as compilation to FPGA-based reconfigurable computing is concerned.

Idioma: Inglês

Tipo (Avaliação Docente): Científica