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Publications with the same authors as the Dynamic Partial Reconfiguration of Customized Single-Row Accelerators publication

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Article in International Scientific Journal

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems
João Bispo (Author) (Other); Nuno Paulino (Author) (FEUP); João Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)
Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units
João Bispo (Author) (Other); Nuno Paulino (Author) (FEUP); João Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)
Optimizing OpenCL Code for Performance on FPGA: k-Means Case Study With Integer Data Sets
Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2020
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Improving Performance and Energy Consumption in Embedded Systems via Binary Acceleration: A Survey
Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2020
Indexing
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2017
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A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
Nuno Paulino (Author) (Other); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2015
Indexing
A Binary Translation Framework for Automated Hardware Generation
Nuno Paulino (Author) (FEUP); João Bispo (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2021
Indexing

Article in International Conference Proceedings Book

Transparent Acceleration of Program Execution Using Reconfigurable Hardware
Nuno Paulino (Author) (Other); João Canas Ferreira (Author) (FEUP); João Bispo (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2015
Indexing
Trace-Based Reconfigurable Acceleration with Data Cache and External Memory Support
Nuno Paulino (Author) (Other); João Canas Ferreira (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2014
Indexing
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
Santos, T (Author) (Other); Nuno Paulino (Author) (FEUP); João Bispo (Author) (FEUP); João M. P. Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)
2021
Indexing
From Instruction Traces to Specialized Reconfigurable Arrays
João Bispo (Author) (Other); Nuno Paulino (Author) (FEUP); João M. P. Cardoso (Author) (FEUP); João Canas Ferreira (Author) (FEUP)
Executing ARMv8 Loop Traces on Reconfigurable Accelerator via Binary Translation Framework
Nuno Paulino (Author) (FEUP); João Canas Ferreira (Author) (FEUP); João Bispo (Author) (FEUP); João M. P. Cardoso (Author) (FEUP)
2020
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