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Transparent Acceleration of Program Execution Using Reconfigurable Hardware

Title
Transparent Acceleration of Program Execution Using Reconfigurable Hardware
Type
Article in International Conference Proceedings Book
Year
2015
Conference proceedings International
Pages: 1066-1071
2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
9 March 2015 through 13 March 2015
Other information
Authenticus ID: P-00G-6B9
Abstract (EN): The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program portability over different target reconfigurable fabrics. However, the problem is very challenging, as suitable sequences of GPP instructions need to be translated/mapped to hardware, possibly at runtime. Thus, all mapping steps, from compiler analysis and optimizations to hardware generation, need to be both efficient and fast. This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hardware, and presents our binary acceleration approach and the latest results. Our approach extends a GPP with a Reconfigurable Processing Unit (RPU), both sharing the data memory. Repeating sequences of GPP instructions are migrated to an RPU composed of functional units and interconnect resources, and able to exploit instruction-level parallelism, e.g., via loop pipelining. Although we envision a fully dynamic system, currently the RPU resources are selected and organized offline using execution trace information. We present implementation prototypes of the system on a Spartan-6 FPGA with a MicroBlaze as GPP and the very encouraging results achieved with a number of benchmarks.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 6
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