Abstract (EN):
Dependability is a critical factor in computer
systems, requiring high quality validation &
verification procedures in the development stage. At
the same time, digital devices are getting smaller and
access to their internal signals and registers is
increasingly complex, requiring innovative debugging
methodologies. To address this issue, most recent
microprocessors include an on-chip debug (OCD)
infrastructure to facilitate common debugging
operations. This paper proposes an enhanced OCD
infrastructure with the objective of supporting the
verification of fault-tolerant mechanisms through fault
injection campaigns. This upgraded On-Chip Debug
and Fault Injection (OCD-FI) infrastructure provides
an efficient fault injection mechanism with improved
capabilities and dynamic behavior. Preliminary results
show that this solution provides flexibility in terms of
fault triggering and allows high speed real-time fault
injection in memory elements.
Language:
English
Type (Professor's evaluation):
Scientific
No. of pages:
6
License type: