Publications with the same journal as the Run-time generation of partial FPGA configurations for subword operations publication

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Another Publication in an International Scientific Journal

MICPRO DSD 2015 special issue

João Canas Ferreira (Author) (FEUP); Kitsos, P (Author) (Other)

2017

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Article in International Scientific Journal

The VALU3S ECSEL project: Verification and validation of automated systems safety and security

Agirre, JA (Author) (Other); Etxeberria, L (Author) (Other); Barbosa, R (Author) (Other); Basagiannis, S (Author) (Other); Giantamidis, G (Author) (Other); Bauer, T (Author) (Other); Ferrari, E (Author) (Other); Esnaola, ML (Author) (Other); Orani, V (Author) (Other); Öberg, J (Author) (Other); Pereira, D (Author) (Other); Proença, J (Author) (Other); Schlick, R (Author) (Other); Smrcka, A (Author) (Other); Tiberti, W (Author) (Other); Tonetta, S (Author) (Other); Bozzano, M (Author) (Other); Yazici, A (Author) (Other); Sangchoolie, B (Author) (Other)

2021

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The ANTAREX domain specific language for high performance computing

Silvano, C (Author) (Other); Agosta, G (Author) (Other); Bartolini, A (Author) (Other); Beccari, AR (Author) (Other); Benini, L (Author) (Other); Besnard, L (Author) (Other); João Bispo (Author) (FEUP); Cmar, R (Author) (Other); João M. P. Cardoso (Author) (FEUP); Cavazzoni, C (Author) (Other); Cesarini, D (Author) (Other); Cherubin, S (Author) (Other); Ficarelli, F (Author) (Other); Gadioli, D (Author) (Other); Golasowski, M (Author) (Other); Libri, A (Author) (Other); Martinovic, J (Author) (Other); Palermo, G (Author) (Other); Pinto, P (Author) (Other); Rohou, E (Author) (Other)...(mais 2 authors)

2019

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Real-time fault injection using enhanced on-chip debug infrastructures

José Martins Ferreira (Author) (FEUP); André V. Fidalgo (Author) (Other); Manuel G. Gericota (Author) (Other); Gustavo R. Alves (Author) (Other)

2011

Scientific classification Indexing Documents

File name	Description	Size
8.J-MM_2011		587.98 KB

Pipelining data-dependent tasks in FPGA-based multicore architectures

Azarian, A (Author) (Other); João M. P. Cardoso (Author) (FEUP)

2016

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Controlling a complete hardware synthesis toolchain with LARA aspects

João M. P. Cardoso (Author) (FEUP); Carvalho, T (Author) (Other); Coutinho, JGF (Author) (Other); Nobre, R (Author) (Other); Nane, R (Author) (Other); Diniz, PC (Author) (Other); Petrov, Z (Author) (Other); Luk, W (Author) (Other); Bertels, K (Author) (Other)

2013

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