Implementation of IEEE-1588 timing and synchronization for ATCA control and data acquisition systems

• Tipo: Artigo em Revista Científica Internacional
• Data: 2012

Autores

Correia, M (Autor) Outra; Sousa, J (Autor) Outra; Combo, A (Autor) Outra; Rodrigues, AP (Autor) Outra; Carvalho, BB (Autor) Outra; Batista, AJN (Autor) Outra; Goncalves, B (Autor) Outra; Correia, CMBA (Autor) Outra; Varandas, CAF (Autor) Outra

Revista

Título: Fusion Engineering and Design

Vol. 87

Páginas: 2178-2181

ISSN: 0920-3796

Editora: Elsevier

Indexação

ISI Web of Knowledge - 6 Citações

Scopus - 8 Citações

Outras Informações

ID Authenticus: P-002-2HD

DOI: 10.1016/j.fusengdes.2012.07.012

Abstract (EN): Control and data acquisition (C&DA) systems for Fusion experiments are required to provide accurate timing and synchronization (T&S) signals to all of its components. IPFN adopted PICMG's Advanced Telecommunications Computing Architecture (ATCA) industry standard to develop C&DA instrumentation. ATCA was chosen not only for its high throughput characteristics but also for its high availability (HA) features which become of greater importance in steady-state operation scenarios. However, the specified ATCA clock and synchronization interface may be too limited for the timing and synchronization needs in advanced Physics experiments. Upcoming specification extensions, developed by the "xTCA for Physics" workgroups, will contemplate, among others, a complementary timing specification, developed by the PICMG xTCA for Physics IO, Timing and Synchronization Technical Committee. The IEEE-1588 Precision Time Protocol (PTP) over Ethernet is one of the protocols, proposed by the Committee, aiming for precise synchronization of clocks in measurement and control systems, based on low jitter and slave-to-slave skew criteria. The paper presents an implementation of IEEE-1588 over Ethernet, in an ATCA hardware platform. The ATCA hardware consists of an Advanced Mezzanine Card (AMC) quad-carrier front board with PCI Express switching. IEEE-1588 is to be implemented on a Virtex-6 FPGA. Ethernet connectivity with the remote master clock is located on the rear transition module (RIM). The generated synchronized clock and absolute time in IRIG-B format are distributed to all systems endpoints by a cross-point switch which is also implemented on the FPGA.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4