Flexible use of IP gores on dynamically reconfigurable systems

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2008

Autores

Miguel L. Silva (Autor) FEUP; João Canas Ferreira (Autor) FEUP; José Silva Matos (Autor) FEUP

Ata de Conferência Internacional

Título: Proceedings of the XXIII Conference on Design of Circuits and Integrated Systems

Páginas: 1-6

XXIII Conference on Design of Circuits and Integrated Systems (DCIS'2008)

Grenoble, França, 12 a 14 de novembro de 2008

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

Abstract (EN): The advantages of dynamic reconfiguration can only be exploited if devices, tools and design flows are available to support the partial reconfiguration of FPGA-based systems. For a number of applications, enabling the swap of cores at run-time, under software control, is an essential feature that allows tailoring the system response to the needs of different methods, standards and power/performance requirements. The paper proposes a method to support the exchange of intellectual property (IP) cores during system operation. The approach is based on the definition of a base system, with reserved or dynamic areas, where different cores may be plugged in, providing timesharing of the system resources. It is shown how bitstream-level IP cores can be used in a design flow that allows different cores to be used in one or more host areas, with minimal intervention from the designer. A demonstration system along with example applications are presented to illustrate the approach.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 6