Transparent runtime migration of loop-based traces of processor instructions to reconfigurable processing units

• Tipo: Artigo em Revista Científica Internacional
• Data: 2013

Autores

João Bispo (Autor) Outra; Nuno Paulino (Autor) FEUP; João Cardoso (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Revista

Título: International Journal of Reconfigurable Computing

Vol. 2013

Páginas: 1-20

ISSN: 1687-7195

Editora: Hindawi

Indexação

Scopus - 7 Citações

INSPEC

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia de computadores

Outras Informações

ID Authenticus: P-008-9TB

DOI: 10.1155/2013/340316

Abstract (EN): The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. In this work, we focus on the mapping of loop-based instruction traces (called Megablocks) to RPUs. The proposed approach considers offline partitioning and mapping stages without ignoring their future runtime applicability. We present a toolchain that automatically extracts specific trace-based loops, called Megablocks, from MicroBlaze instruction traces and generates an RPU for executing those loops. Our hardware infrastructure is able to move loop execution from the microprocessor to the RPU transparently, at runtime, and without changing the executable binaries. The toolchain and the system are fully operational. Three FPGA implementations of the system, differing in the hardware interfaces used, were tested and evaluated with a set of 15 application kernels. Speedups ranging from 1.26 × to 3.69 × were achieved for the best alternative using a MicroBlaze processor with local memory. © 2013 João Bispo et al.

Idioma: Inglês

Tipo (Avaliação Docente): Científica