A Comparison of Three Representative Hardware Sorting Units

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2009

Autores

Rui Marcelino (Autor) Outra; Horácio C. Neto (Autor) Outra; João M. P. Cardoso (Autor) FEUP

Ata de Conferência Internacional

Título: IECON: 2009 35TH ANNUAL CONFERENCE OF IEEE INDUSTRIAL ELECTRONICS, VOLS 1-6

Páginas: 2643-2648

35th Annual Conference of the IEEE-Industrial-Electronics-Society (IECON 2009)

Porto, PORTUGAL, NOV 03-05, 2009

Indexação

ISI Web of Knowledge - 2 Citações

Scopus - 14 Citações

INSPEC

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia de computadores

Outras Informações

ID Authenticus: P-003-QFQ

DOI: 10.1109/iecon.2009.5415409

Abstract (EN): Sorting is an important operation for many embedded computing systems. Since sorting large datasets may slowdown the overall execution, schemes to speedup sorting operations are needed. Bearing in mind the hardware acceleration of sorting, we show in this paper an analysis and comparison among three hardware sorting units: Sorting Network, Insertion Sorting, and FIFO-based Merge Sorting. We focus on embedded computing systems implemented with FPGAs, which give us the flexibility to accommodate customized hardware sorting units. We also present a hardware/software solution for sorting data sets with size larger than the size of the sorting unit. This hardware/software solution achieves 20x overall speedup over a pure software implementation of the well-known quicksort algorithm.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 6