Partial Dynamic Reconfiguration of Multi-Stage Networks in FPGAs

• Tipo: Artigo em Livro de Atas de Conferência Nacional
• Data: 2012

Autores

Joao Santos (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Ata de Conferência Nacional

Título: Actas das VIII Jornadas sobre Sistemas Reconfiguráveis (REC 2012)

Páginas: 115-120

VIII Jornadas sobre Sistemas Reconfiguráveis (REC 2012)

Lisboa, Portugal, 9 a 10 de Fevereiro de 2012

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrónica

Outras Informações

Abstract (EN): This paper reports the results of a project in-tended to study the impact of partial dynamic re-configuration in the performance of multi-stage interconnection networks (MINs) in FPGAs. The MIN connections can be changed by partial dy-namic reconfiguration without affecting the rest of the hardware which is connected to the network. The time required to change the connections with partial dynamic reconfiguration is bigger than the time required for routing data. The main trade-off of this approach is between the routing time re-quired to change the network connections and the MIN’s area and latency, which are reduced by the specialization afforded by partial dynamic recon-figuration. This work studies Omega networks with eight inputs and out-puts with one, two, four and eight-bit wide ports. Versions of these networks with and without support of partial dynamic reconfiguration were developed for use on a Virtex-II Pro FPGA (XCV2P30). Areas and delays were measured, together with the size of the partial bitstreams required for modifying the interconnection pattern and to add or remove stages in these networks. The reconfiguration times were computed for a configuration access port frequency of 50 MHz.

Idioma: Inglês

Tipo (Avaliação Docente): Científica