Using FPGAs for Real-Time Disparity Map Calculation

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2010

Autores

Carlos Resende (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Ata de Conferência Internacional

Título: DCIS 2010

Páginas: 625-630

XXV Conference on Design of Circuits and Integrated Systems

Lanzarote, Spain, 17 a 19 de Novembro de 2010

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrónica ; Ciências Tecnológicas > Engenharia > Engenharia de computadores

Outras Informações

Abstract (EN): Real-time stereo image matching is an important computer vision task. This paper presents the architecture and implementation of an FPGA-based stereo image processor, that produces 25 dense depth maps per second from pairs of 8-bit-per pixel gray-scale images. The system implements a modification of a previously-reported variable-window-size method to determine the best correspondence for each image pixel. The degree of parallelism of the implementation can be adapted to the available resources: increased parallelism enables the processing of larger images (at the same frame rate). The proposed architecture exploits the memory resources available in modern platform FPGAs. Two prototype implementations have been produced and validated: the smaller one can handle pairs of images of size 208x480 , while the larger one works for images of size 640x480 (both operate at 100 MHz). These results improve on previously-reported ASIC and FPGA-based designs.

Idioma: Inglês

Tipo (Avaliação Docente): Científica