A vector architecture for higher-order moments estimation

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 1997

Autores

José Carlos Alves (Autor) FEUP; Puga, A (Autor) Outra; Luís Corte-Real (Autor) FEUP; Matos, JS (Autor) Outra

Ata de Conferência Internacional

Título: 1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS

Páginas: 4145-4148

1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 97)

MUNICH, GERMANY, APR 21-24, 1997

Indexação

ISI Web of Knowledge - 0 Citações

Scopus - 1 Citação

Outras Informações

ID Authenticus: P-001-D3E

Abstract (EN): Higher-order statistics extend the analysis methods of non-linear systems and non-gaussian signals based on the autocorrelation and power spectrum. The main drawback of their use in real time applications is the high complexity of their estimation due to the large number of arithmetic operations. This paper presents an experimental vector architecture for the estimation of the higher-order moments. The processor's core is a pipelined multiply-accumulate unit that receives four data vectors and computes in parallel the moment taps up to the fourth-order. The design of custom cache memory organization and address generation circuits has led to more than 11 operations per clock cycle. The architecture was modeled and simulated in Verilog and is presently being implemented in XILINX field-programmable gate arrays (FPGAs) and one custom integrated circuit for the multiply-accumulate unit.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4