Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing System

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 1999

Autores

João M. P. Cardoso (Autor) Outra; Neto, HC (Autor) Outra

Ata de Conferência Internacional

Título: IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Páginas: 2-11

Proceedings of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCMM 1999)

Napa Valley, CA, 21 April 1999 through 23 April 1999

Indexação

Scopus - 30 Citações

Outras Informações

ID Authenticus: P-007-8WD

DOI: 10.1109/FPGA.1999.803662

Abstract (EN): This paper presents a new approach to synthesize to reconfigurable hardware (HW) user-specified regions of a program, under the assumption of "virtual HW" support. The automation of this approach is supported by a compiler front-end and by an HW compiler under development. The front-end starts from the Java bytecodes and, therefore, supports any language that can be compiled to the JVM (Java Virtual Machine) model. It extracts from the bytecodes all the dependencies inside and between basic blocks. This information is stored in representation graphs more suitable to efficiently exploit the existent parallelism in the program than those typically used in high-level synthesis. From the intermediate representations the HW compiler exploits the temporal partitions at the behavior level, resolves memory access conflicts, and generates the VHDL descriptions at register-transfer level that will be mapped into the reconfigurable HW devices.

Idioma: Inglês

Tipo (Avaliação Docente): Científica