GENERATION OF PARTIAL FPGA CONFIGURATIONS AT RUN-TIME

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2008

Autores

Miguel L. Silva (Autor) FEUP; João Canas Ferreira (Autor) FEUP

Ata de Conferência Internacional

Título: 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2

Páginas: 366-371

International Conference on Field Programmable and Logic Applications

Heidelberg, GERMANY, SEP 08-10, 2008

Indexação

ISI Web of Knowledge - 2 Citações

Scopus - 11 Citações

Classificação Científica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

ID Authenticus: P-004-5EQ

DOI: 10.1109/fpl.2008.4629965

Abstract (EN): The paper presents a method for generating partial bitstreams on-line for use in systems with run-time reconfigurable FPGAs. Bitstream creation is performed at run-time by merging partial bitstreams from individual component modules. The process includes the capability to create connections between the modules by selection from a set of routes found during an off-line pre-processing step. Placement and interconnection of modules must follow a precise set of rules. While restricting the number of possible module arrangements, this approach allows bitstream, creation to be performed with relatively few computational resources. Using a demonstration system with a Virtex-II Pro FPGA with a PowerPC 405 CPU, the process of creating at run-time a partial bitstream for 22% of the device area takes 24 ms.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 6