GENERATION OF PARTIAL FPGA CONFIGURATIONS AT RUN-TIME

• Type: Article in International Conference Proceedings Book
• Date: 2008

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings International

Title: 2008 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE AND LOGIC APPLICATIONS, VOLS 1 AND 2

Pages: 366-371

International Conference on Field Programmable and Logic Applications

Heidelberg, GERMANY, SEP 08-10, 2008

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 11 Citations

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Authenticus ID: P-004-5EQ

DOI: 10.1109/fpl.2008.4629965

Abstract (EN): The paper presents a method for generating partial bitstreams on-line for use in systems with run-time reconfigurable FPGAs. Bitstream creation is performed at run-time by merging partial bitstreams from individual component modules. The process includes the capability to create connections between the modules by selection from a set of routes found during an off-line pre-processing step. Placement and interconnection of modules must follow a precise set of rules. While restricting the number of possible module arrangements, this approach allows bitstream, creation to be performed with relatively few computational resources. Using a demonstration system with a Virtex-II Pro FPGA with a PowerPC 405 CPU, the process of creating at run-time a partial bitstream for 22% of the device area takes 24 ms.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 6