A boundary scan test controller for hierarchical BIST

• Type: Article in International Conference Proceedings Book
• Date: 1992

Authors

José S. Matos (Author) FEUP; Filipe S. Pinto (Author) Other; José M. M. Ferreira (Author) FEUP

Conference proceedings International

Title: Proceedings of the IEEE International Test Conference

Pages: 217-223

IEEE International Test Conference

Baltimore, USA, 24 - SETEMBRO - 1992

Indexing

ISI Web of Science

Scopus

INSPEC

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

DOI: 10.1109/TEST.1992.527822

Abstract (EN): A test controller for BIST of Boundary Scan Boards is described. It consists of a test processor core, with an optimized architecture for controlling the board-level BST infrastructure, and a system level testability bus interjace, allowing the implementation of a hierarchical test strategy. Automatic test pattern generation for this dedicated processor simplifies the task of providing a board-level BIST solution.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 7