A modular architecture for BIST of boundary scan boards

• Type: Article in International Conference Proceedings Book
• Date: 1992

Authors

José M. M. Ferreira (Author) FEUP; Filipe S. Pinto (Author) Other; José S. Matos (Author) FEUP

Conference proceedings International

Title: Proceedings of the EUROASIC Conference

Pages: 184-188

EUROASIC Conference

Paris, França, 02 - JUNHO - 1992

Indexing

INSPEC

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

DOI: 10.1109/EUASIC.1992.228027

Abstract (EN): A board-level BIST architecture for boards loaded with ASICs and VLSI components, compliant with the IEEE 1149.1 BST standard, is described. This BIST architecture consists of a test processor core, with an optimized architecture for controlling the board-level BST (boundary scan test) infrastructure, an optional system-level testability bus interface, to be included when a system-level test strategy is to be implemented, and a ROM containing the test program, which is automatically generated by an ATPG tool.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 5