A framework for fault tolerant real time systems based on reconfigurable FPGAs

• Type: Article in International Conference Proceedings Book
• Date: 2006-09

Authors

José M. Ferreira (Author) FEUP; Manuel G. Gericota (Author) Other; Luís F. Lemos (Author) Other; Gustavo R. Alves (Author) Other; Mário M. Barbosa (Author) Other

Conference proceedings International

Title: 2006 IEEE CONFERENCE ON EMERGING TECHNOLOGIES & FACTORY AUTOMATION, VOLS 1 -3

Pages: 131-138

11th IEEE International Conference on Emerging Technologies and Factory Automation

Prague, CZECH REPUBLIC, SEP 20-22, 2006

Indexing

ISI Web of Science

Scopus

INSPEC

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

DOI: 10.1109/ETFA.2006.355409

Abstract (EN): To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 8