High Level Language Specification of TPG Procedures for F-BST Boards, relatório D4.2

• Type: Technical Report
• Date: 1990

Authors

José Martins Ferreira (Author) FEUP; José Silva Matos (Author) FEUP; F. Jong (Author) Other

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): This document presents a high level pseudocode specification of a set of test pattern generation (TPG) procedures for testing interconnects in boards loaded exclusively with BST components, where more than one BST chain may exist. The characteristics of the adopted board-level fault model are briefly described. Open, stuck-at and short faults are considered, and the underlying technology related assumptions are presented. For interconnect short testing, a two-step algorithm is presented. In the first step, a minimum size set of test patterns (TPs) with full fault detection capability is used. The concept of Eventually Puzzling Syndromes is introduced and is used to specify a reduced complexity second step, allowing complete fault location. The TPG procedures for detection and diagnosis of the various fault types are presented in a high level C language type pseudocode.

Language: Portuguese

Type (Professor's evaluation): Scientific

No. of pages: 31