Hardware/software compilation

• Type: Chapter or Part of a Book
• Date: 2013

Authors

Ricardo Nobre (Author) Other; João M. P. Cardoso (Author) FEUP; Bryan Olivier (Author) Other; Razvan Nane (Author) Other; Liam Fitzpatrick (Author) Other; José Gabriel de F. Coutinho (Author) Other; Hans van Someren (Author) Other; Vlad-Mihai Sima (Author) Other; Koen Bertels (Author) Other; Pedro C. Diniz (Author) Other

Book

Title: Compilation and Synthesis for Embedded Reconfigurable Systems: An Aspect-Oriented Approach

Pages: 105-134

ISBN: 978-1-4614-4893-8

Electronic ISBN: 978-1-4614-4894-5

Publisher: Springer

Indexing

Scopus - 1 Citation

Other information

Authenticus ID: P-00G-5M8

DOI: 10.1007/978-1-4614-4894-5-5

Abstract (EN): This chapter describes the CoSy1-based [1, 2] compilers developed in the context of the REFLECT project to support its aspect-oriented design-flow. In particular, these CoSy-based compilers are guided by LARA strategies and are responsible for generating code targeting traditional processors, as well as generating behavioral-RTL VHDL code [3] targeting hardware accelerators. Throughout this chapter, these compilers are referred collectively as reflectc, except when a specific compilation flow (with its specific name) is used. We also describe the compiler development extensions to support the REFLECT approach [4] and the weaving process controlled by LARA strategies [5-7] as described in Chap. 3. © Springer Science+Business Media New York 2013. All rights are reserved.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 30