FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2021

Autores

Silva, PF (Autor) Outra; João Bispo (Autor) FEUP; Nuno Paulino (Autor) FEUP

Ata de Conferência Internacional

Título: International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021

Páginas: 102-105

20th International Conference on Field-Programmable Technology, ICFPT 2021

6 December 2021 through 10 December 2021

Indexação

ISI Web of Knowledge - 1 Citação

Scopus - 2 Citações

Outras Informações

ID Authenticus: P-00V-V3R

DOI: 10.1109/icfpt52863.2021.9609832

Abstract (EN): We discuss the concept of FPGA-unfriendliness, the property of certain algorithms, programs, or domains which may limit their applicability to FPGAs. Specifically, we look at graph analysis, which has recently seen increased interest in combination with High-Level Synthesis, but has yet to find great success compared to established acceleration mechanisms. To this end, we make use of Xilinx's Vitis Graph Library to implement Single-Source Shortest Paths (SSSP) and PageRank (PR), and present a custom kernel written from the ground up for Distinctiveness Centrality (DC, a novel graph centrality measure). We use public datasets to test these implementations, and analyse power consumption and execution time. Our comparisons against published data for GPU and CPU execution show FPGA slowdowns in execution time between around 18.5x and 328x for SSSP, and around 1.8x and 195x for PR, respectively. In some instances, we obtained FPGA speedups versus CPU of up to 2.5x for PR. Regarding DC, results show speedups from 0.1x to 3.5x, and energy efficiency increases from 0.8x to 6x. Lastly, we provide some insights regarding the applicability of FPGAs in FPGA-unfriendly domains, and comment on the future as FPGA and HLS technology advances.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4