| Summary: |
ln the last few years, Application Specific lntegrated Circuits (ASICs), because of their long design and development time, escalating development costs and low flexibility, were increasingly restricted to high-volume manufacturing of chips requiring cutting edge-of-the-technology densities and speed processing.
Meanwhile, the exponential growth in density and performance of configurable logic devices, such as SRAM-based Field Programmable Gate Arrays (FPGAs), greatly expanded the areas where these devices can advantageously replace ASICs. FPGAs have lower development costs, faster time-to-market, and an unparalleled flexibility.
Recently, two new features were added: i) dynamic reconfiguration, enabling real-time dynamic resource allocation strategies (multiple independent functions from different applications may now share the same logic resources in the space and temporal domain), and; ii) self-reconfiguration, enabling self-adaptation of the FPGA (new functional requirements may now be satisfied autonomously, without intervention of a controller external to the FPGA).
These new FPGA devices may be used in a wide range of applications, such as reconfigurable hardware platforms, but create new challenges as well, namely in terms of reliability and test. The nanometre technologies increase their vulnerability to soft errors, due to environmental radiation, and make them more prone to defects emerging from small manufacturing imperfections that are not detected during production tests. These imperfections are a potential problem, since they may originate transient or permanent changes in the functional configuration of the device. The increasing use of reconfigurable FPGAs, namely in criticaI systems, therefore requires the design of fault tolerant circuits able to assure high levels of reliability and availability. This goal demands online concurrent detection of permanent and transient faults, which should be masked to avoid propagation, while triggering a t  |
Summary
ln the last few years, Application Specific lntegrated Circuits (ASICs), because of their long design and development time, escalating development costs and low flexibility, were increasingly restricted to high-volume manufacturing of chips requiring cutting edge-of-the-technology densities and speed processing.
Meanwhile, the exponential growth in density and performance of configurable logic devices, such as SRAM-based Field Programmable Gate Arrays (FPGAs), greatly expanded the areas where these devices can advantageously replace ASICs. FPGAs have lower development costs, faster time-to-market, and an unparalleled flexibility.
Recently, two new features were added: i) dynamic reconfiguration, enabling real-time dynamic resource allocation strategies (multiple independent functions from different applications may now share the same logic resources in the space and temporal domain), and; ii) self-reconfiguration, enabling self-adaptation of the FPGA (new functional requirements may now be satisfied autonomously, without intervention of a controller external to the FPGA).
These new FPGA devices may be used in a wide range of applications, such as reconfigurable hardware platforms, but create new challenges as well, namely in terms of reliability and test. The nanometre technologies increase their vulnerability to soft errors, due to environmental radiation, and make them more prone to defects emerging from small manufacturing imperfections that are not detected during production tests. These imperfections are a potential problem, since they may originate transient or permanent changes in the functional configuration of the device. The increasing use of reconfigurable FPGAs, namely in criticaI systems, therefore requires the design of fault tolerant circuits able to assure high levels of reliability and availability. This goal demands online concurrent detection of permanent and transient faults, which should be masked to avoid propagation, while triggering a test procedure to determine their origin, either functional or structural, and to assure the repair of their cause(s), avoiding cumulative effects that may lead to a general system failure.
Therefore, it becomes imperative to study the specific fault inducement mechanisms of these devices and to develop innovative test methodologies tailored to their unique architecture and to the new applications that are now possible. Such methodologies have to guarantee both fault tolerance and repair, by detecting faulty resources, and also to avoid their use when new incoming functions required by the applications sharing the FPGA are implemented.
The incorporation of self-reconfiguration capabilities in recent FPGAs, together with an embedded controller core, enables the development of self-fault-tolerant reconfigurable systems. The on-chip controller will be responsible for all rerouting and floorplanning operations, enabling the implementation of fault detection, test and repair procedures in a transparent and autonomous way. |