A Wrapper for Testing Analogue to Digital Converters Cores in SoCs

• Type: Article in International Conference Proceedings Book
• Date: 2004

Authors

Joana A. Braga (Author) FEUP; José Machado da Silva (Author) FEUP; José C. Alves (Author) FEUP; José S. Matos (Author) FEUP

Conference proceedings International

Title: Informal Digest of Papers of the 9th IEEE European Test Symposium

Pages: 170-175

9th IEEE European Test Symposium

Corsica, France, May 23-26, 2004

Other information

Abstract (EN): The specification and description of a wrapper for testing analogue to digital converters embedded in integrated systems is presented. The proposed wrapper architecture is compatible with standard test buses IEEE 1149.1/4 and complies also with the IEEE P1500 standard proposal. Data pre-processing logic built-in the wrapper allows reducing testing time because a small number of values is up-loaded to the tester for further processing to obtain total harmonic characterization parameters. A three line parallel bus comprising two analogue lines and a clock signal is used as test output data is uploaded by means the serial bus.

Language: Portuguese

Type (Professor's evaluation): Scientific

No. of pages: 6