Hardware architecture for integrate-and-fire signal reconstruction on FPGA

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2020

Autores

Carvalho, G (Autor) Outra; João Canas Ferreira (Autor) FEUP; Vítor Grade Tavares (Autor) FEUP

Ata de Conferência Internacional

Título: 2020 XXXV Conference on Design of Circuits and Integrated Systems (DCIS)

Páginas: 1-6

Indexação

ISI Web of Knowledge - 0 Citações

Scopus - 1 Citação

Outras Informações

ID Authenticus: P-00T-394

DOI: 10.1109/dcis51330.2020.9268638

Abstract (EN): Typical analogue-to-digital conversion (ADC) architectures, at Nyquist rate, tend to occupy a big portion of the integrated circuit die area and to consume more power than desired. Recently, with the rise of Interet-of-Things (IoT), there is a high demand for architectures that can have both reduced area and power consumption. Time encoding machines (TEM) might be a promising alternative. These types of encoders result in very simple and low-power analogue circuits, shifting most of its complexity to the decoding stage, typically stationed in a place with access to more resources. This paper focuses on a particular TEM, the integrate-and-fire neuron (IFN). The IFN modulation is based on a simplified first-order model of neural operation and it encodes the signal in a very power efficient manner. In the end, a novel hardware architecture for the reconstruction of the IFN encoded signal based on a spiking model will be presented. The method is demonstrated and implemented on FPGA, reaching an ENOB as high as 8.23.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 6