Run-time generation of partial FPGA configurations

• Type: Article in International Scientific Journal
• Date: 2012

Authors

Silva, ML (Author) Other; João Canas Ferreira (Author) FEUP

Journal

Title: Journal of Systems Architecture

Vol. 58

Pages: 24-37

ISSN: 1383-7621

Publisher: Elsevier

Indexing

ISI Web of Knowledge - 1 Citation

Scopus - 2 Citations

Other information

Authenticus ID: P-002-H40

DOI: 10.1016/j.sysarc.2011.10.001

Abstract (EN): This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 14