Flexible use of IP gores on dynamically reconfigurable systems

• Type: Article in International Conference Proceedings Book
• Date: 2008

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP; José Silva Matos (Author) FEUP

Conference proceedings International

Title: Proceedings of the XXIII Conference on Design of Circuits and Integrated Systems

Pages: 1-6

XXIII Conference on Design of Circuits and Integrated Systems (DCIS'2008)

Grenoble, França, 12 a 14 de novembro de 2008

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): The advantages of dynamic reconfiguration can only be exploited if devices, tools and design flows are available to support the partial reconfiguration of FPGA-based systems. For a number of applications, enabling the swap of cores at run-time, under software control, is an essential feature that allows tailoring the system response to the needs of different methods, standards and power/performance requirements. The paper proposes a method to support the exchange of intellectual property (IP) cores during system operation. The approach is based on the definition of a base system, with reserved or dynamic areas, where different cores may be plugged in, providing timesharing of the system resources. It is shown how bitstream-level IP cores can be used in a design flow that allows different cores to be used in one or more host areas, with minimal intervention from the designer. A demonstration system along with example applications are presented to illustrate the approach.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 6