Exploiting dynamic reconfiguration of platform FPGAs: implementation issues

• Type: Article in International Conference Proceedings Book
• Date: 2006

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings International

Title: 20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Pages: 1-8

Indexing

Scopus - 2 Citations

INSPEC

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electrical engineering

Other information

Authenticus ID: P-007-H2M

DOI: 10.1109/ipdps.2006.1639447

Abstract (EN): The effective use of dynamic reconfiguration requires the designer to address many implementation issues. The market introduction of feature-full platform FPGAs equipped with embedded CPU blocks expands the number of situations where dynamic reconfiguration may be applied to improve overall performance and logic utilization. The paper compares the design of two similar systems supporting dynamic reconfiguration and the issues that were addressed in their implementation. The first system supports 32-bit data transfers between CPU and the dynamically reconfigurable circuits. The other implementation supports 64-bit transfers, but its effective use is more complicated and several restrictions must be taken into account. The work includes a performance comparison of the two designs on several simple tasks, including pattern matching, image processing and hashing. © 2006 IEEE.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 8