Automatic generation of a single-chip solution for board-level BIST of boundary scan boards

• Type: Article in International Conference Proceedings Book
• Date: 1992

Authors

José M. M. Ferreira (Author) FEUP; Filipe S. Pinto (Author) Other; José S. Matos (Author) FEUP

Conference proceedings International

Title: Proceedings of the European Design Automation Conference

Pages: 154-158

EDAC - European Design Automation Conference

Bruxelas, Bélgica, 16 - MARÇO - 1992

Indexing

INSPEC

Scientific classification

CORDIS: Technological sciences > Engineering > Electrical engineering

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

DOI: 10.1109/EDAC.1992.205913

Abstract (EN): The automatic generation of a hierarchical self-test architecture for boards with boundary scan test (BST) is described, based on a test processor specifically designed to implement the basic operations required to control the BST infrastructure. An ATPG module generates the ROM containing the test program, allowing a single-chip self-test solution with minimal design-for-testability overhead. The same test processor may be used without internal ROM, when a single-chip solution is not desirable.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 5