Run-time Generation of Partial Configurations for Arithmetic Expressions

• Type: Article in International Conference Proceedings Book
• Date: 2010

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP; Miguel L. Silva (Author) FEUP

Conference proceedings International

Title: 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS

Pages: 117-120

53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)

Seattle, WA, AUG 01-04, 2010

Indexing

ISI Proceedings

ISI Web of Knowledge - 3 Citations

Scopus - 0 Citations

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electronic engineering ; Technological sciences > Engineering > Computer engineering

Other information

Authenticus ID: P-003-DG5

DOI: 10.1109/mwscas.2010.5548575

Abstract (EN): Adaptive embedded systems can achieve enhanced flexibility by performing run-time reconfiguration of hardware. This paper describes a method to generate at run-time new partial FPGA configurations corresponding to arithmetic expressions. This is achieved by merging available partial bitstreams of arithmetic components to produce a new partial bitstream for a specific FPGA area. The connections among the components are mapped to the switch matrices of the reconfigurable fabric, and the corresponding information is added to the new partial configuration. The proposed method was implemented for a Virtex-II Pro FPGA with a 300 MHz PowerPC 405 CPU. It was used to create partial configurations in less than 69 s for sets of arithmetic circuits with up to 25 components and 208 connections.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 4