Run-time Generation of Configurations for Dynamically Reconfigurable Systems

• Type: Article in International Conference Proceedings Book
• Date: 2009

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings National

Title: Actas das V Jornadas sobre Sistemas Reconfiguráveis - REC'2009

Pages: 7-12

V Jornadas sobre Sistemas Reconfiguráveis - REC'2009

Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa, Monte de Caparica, Portugal, 5 a 6 de Fevereiro de 2009

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): The paper describes a process for run-time generation of partial bitstreams on a dynamically reconfigurable FPGA. From the partial bitstreams of each component module, new partial bitstreams are created at run-time, that place and connect the component modules inside a time-shared zone of the FPGA. The process has two methods for placement and creation of the connections between modules. The choice of method is a balance between time required to produce the partial bitstream and placement flexibility. Using the simpler method, placement and interconnection of modules must follow a restrictive set of rules. While limiting the number of possible module arrangements, this approach allows bitstream creation to be performed with relatively few computational resources. In the more flexible approach, a routing algorithm is used to connect the modules according to a simple routing model. This approach allows a more flexible placement of modules but consumes more resources. A Virtex-II-Pro-based demonstration system is used to show the feasibility of the proposed on-line bitstream generation methods.

Language: Portuguese

Type (Professor's evaluation): Scientific