Abstract (EN):
The paper describes the organization and use of a pipeline that is tightly-coupled to the CPU inside a platform FPGA with support for dynamic partial reconfiguration. It describes the overall hardware system organization and the pipeline structure, and presents the associated development environment and run-time support system, including the support for dynamically changing pipeline implementations and altering the operations of a pipeline
stage.
Language:
English
Type (Professor's evaluation):
Scientific
Contact:
jcf@fe.up.pt