Boundary scan test, test methodology, and fault modeling

• Type: Article in International Scientific Journal
• Date: 1991

Authors

Frans de Jong (Author) Other; José S. Matos (Author) FEUP; José M. Ferreira (Author) FEUP

Journal

Title: Journal of Electronic Testing: Theory and Applications (JETTA)

Vol. 2 No. 1

Pages: 77-88

ISSN: 0923-8174

Publisher: Springer Nature

Indexing

Scopus

INSPEC

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electrical engineering

Other information

Abstract (EN): The test technique called "boundary scan test" (BST) offers new opportunities in testing but confronts users with new problems too. The implementation of BST in a chip has become an IEEE standard and users on board level are the next group to begin thinking about using the new possibilities. This article addresses some of the questions about changes in board-level testing and fault diagnosis. The fault model itself is also affected by using BST. Trivial items are extended with more sophisticated details in order to complete the fault model. Finally, BST appears to be a test technique that offers a high degree of detectability on board level, but for diagnosis, some additional effort has to be made.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 12