Hardware/Software Implementation Factors Influencing Ethernet Latency

• Type: Article in International Conference Proceedings Book
• Date: 2018

Authors

Correa, TP (Author) Other; Luis Almeida (Author) FEUP; Bueno Pena, EB (Author) Other

Conference proceedings International

Title: Proceedings - IEEE 16th International Conference on Industrial Informatics, INDIN 2018

Pages: 323-328

16th IEEE International Conference on Industrial Informatics, INDIN 2018

18 July 2018 through 20 July 2018

Indexing

ISI Web of Knowledge - 0 Citations

Scopus - 2 Citations

Other information

Authenticus ID: P-00P-TEF

DOI: 10.1109/indin.2018.8472002

Abstract (EN): Minimum Cycle Time is a common performance indicator adopted to compare Real-Time Ethernet protocols. Though serving its purpose, Minimum Cycle Time excludes the delays inside the sending and receiving nodes, so it is insufficient to estimate the end-to-end latency. In this work, we describe some implementation possibilities of an Ethernet node in a System-on-Chip and present measurements of the delay to send/receive packets from/to the application layer. We chose different points in the software to make the measurement, so the results cover more use-cases. We found the Ethernet Lite Media Access Controller (MAC) to be faster than the hard MAC (GEM) and the Lightweight IP stack to add less than 2.2 mu s. Finally, we show how a hardware accelerator can reduce the delay of high-priority packets by 1.4 mu s.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 6