InGaZnO TFT behavioral model for IC design

• Type: Article in International Scientific Journal
• Date: 2016

Authors

Bahubalindrun, P (Author) Other; Vítor Grade Tavares (Author) FEUP; Barquinha, P (Author) Other; de Oliveira, PG (Author) Other; Martins, R (Author) Other; Fortunato, E (Author) Other

Journal

Title: Analog Integrated Circuits and Signal Processing

Vol. 87

Pages: 73-80

ISSN: 0925-1030

Publisher: Springer Nature

Indexing

ISI Web of Knowledge - 13 Citations

Scopus - 18 Citations

Other information

Authenticus ID: P-00K-B7Q

DOI: 10.1007/s10470-016-0706-4

Abstract (EN): This paper presents a behavioral model for amorphous indium-gallium-zinc oxide thin-film transistor using artificial neural network (ANN) based equivalent circuit (EC) approach to predict static and dynamic behavior of the device. In addition, TFT parasitic capacitances (C-GS and C-GD) characterization through measurements is also reported. In the proposed model, an EC is derived from the device structure, in terms of electrical lumped elements. Each electrical element in the EC is modeled with an ANN. Then these ANNs are connected together as per the EC and implemented in Verilog-A. The proposed model performance is validated by comparing the circuit simulation results with the measured response of a simple common-source amplifier, which has shown 12.2 dB gain, 50 mu W power consumption and 85 kHz 3-dB frequency with a power supply of 6 V. The same circuit is tested as an inverter and its response is also presented up to 50 kHz, from both simulations and measurements. These results show that the model is capable of capturing both small and large signal behavior of the device to good accuracy, even including the harmonic distortion of the signal (that emphasizes the nonlinear behavior of the parasitic capacitance), making the model suitable for IC design.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 8