Mapping and execution optimizations

• Type: Chapter or Part of a Book
• Date: 2008

Authors

João M. P. Cardoso (Author) FEUP; P. C. Diniz (Author) Other

Book

Title: Compilation Techniques for Reconfigurable Architectures

Pages: 109-154

ISBN: 978-0-387-09670-4

Electronic ISBN: 978-0-387-09671-1

Publisher: Springer

Other information

Authenticus ID: P-00G-ZXP

DOI: 10.1007/978-0-387-09671-1_5

Abstract (EN): This chapter describes important aspects related to the mapping of computations to reconfigurable architectures. The inherently spatial nature of these architectures, their heterogeneity and the invariable limitations of its physical resources, makes this mapping an extremely challenging task. Compilers and tools must judiciously balance the use of different kinds of resources in space and time, engaging in algorithmic and mapping techniques similar to the ones used in the context of low level hardware synthesis, albeit with mapping choices that can be leveraged at much higher levels of abstraction. We begin this chapter with control-flow mapping techniques enabled by the spatial nature of the target reconfigurable architectures. Next, we address spatial and temporal partitioning of computations within a single or multiple devices, respectively, followed by high-level techniques to map scalar variables and operations to hardware resources. We then describe memory mapping techniques for high-level data abstractions such as multidimensional arrays or data streams. Finally, and given their importance, we describe pipe lining execution schemes at either fine- or coarse grained levels.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 46