Introduction

• Type: Chapter or Part of a Book
• Date: 2008

Authors

João M. P. Cardoso (Author) FEUP; P. C. Diniz (Author) Other

Book

Title: Compilation Techniques for Reconfigurable Architectures

Pages: 1-6

ISBN: 978-0-387-09670-4

Electronic ISBN: 978-0-387-09671-1

Publisher: Springer

Other information

Authenticus ID: P-00G-ZXJ

DOI: 10.1007/978-0-387-09671-1_1

Abstract (EN): The increasing number of transistors on a chip [221,278] has enabled the emergence of reconfigurable architectures and systems with a wide range of implementation flavors [145, 308]. While they were once confined to glue-logic applications, given their very limited device capacities, reconfigurable architectures now cover a wide range of application domains, including high-performance computing where they deliver complete multicore solutions on a single chip [228, 270, 303]. The diversity of reconfigurable architectures is astounding. At one end of the spectrum, reconfigurable architectures are composed of a very large number of finegrained configurable elements as is the case in Field-Programmable-Gate-Arrays (FPGAs) [5, 14, 54, 111]. In this case, one can build very specialized storage and custom computing elements in response to specific domain requirements such as input data rates or stringent real-time requirements. At the other end of the spectrum, many computing cores such as general-purpose processors (GPPs) can be interconnected with other processors or memory via a customized reconfiguration network [37, 211, 303]. In between these two extremes lies a range of architectural options where multiple, and possibly heterogeneous, custom processing elements and storage structures can be interconnected in an almost infinite set of possibilities [145].

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 6