An infrastructure to functionally test designs generated by compilers targeting FPGAs

• Type: Article in International Conference Proceedings Book
• Date: 2005

Authors

Rodrigues, R (Author) Other; João M. P. Cardoso (Author) Other

Conference proceedings International

Title: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS

Pages: 30-31

Design, Automation and Test in Europe Conference and Exhibition (DATE 05)

Munich, GERMANY, MAR 07-11, 2005

Indexing

ISI Web of Knowledge - 3 Citations

Scopus - 3 Citations

Other information

Authenticus ID: P-000-5HK

DOI: 10.1109/date.2005.60

Abstract (EN): This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 2