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Publications with the same authors as the Boundary Scan Test: Uma Metodologia para o Teste de Sistemas Electrónicos publication

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Technical Report

Verification of TPG Procedures for F-BST Boards, relatório R4.3
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Jong (Author) (Other)
Verification of TPG Procedures for BST Boards with Additional ST-Clusters, relatório R4.4
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Jong (Author) (Other)
Um Processador Dedicado para o Auto-Teste de Cartas de Circuito Impresso com BST (V2.0)
José Martins Ferreira (Author) (FEUP); F. Pinto (Author) (Other); José Silva Matos (Author) (FEUP)
Test Pattern Generation Methodology for Full Boundary Scan Test, relatório D4.1
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Jong (Author) (Other)
Projecto de um Processador para o Auto-Teste de Cartas de Circuito Impresso com BST
José Martins Ferreira (Author) (FEUP); F. Pinto (Author) (Other); José Silva Matos (Author) (FEUP)
Projecto de um ASIC para o Controlo de Tempo e Temperatura em Electrodomésticos
José Martins Ferreira (Author) (FEUP); F. Pinto (Author) (Other); José Silva Matos (Author) (FEUP)
High Level Language Specification of TPG Procedures for F-BST Boards, relatório D4.2
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Jong (Author) (Other)
Especificação da Arquitectura Global, relatório n.º 2 do projecto PMCT/C/TIT/937/90
José Martins Ferreira (Author) (FEUP); António Duarte Araújo (Author) (FEUP); F. Pinto (Author) (Other); J. Tavares (Author) (Other); Gustavo Alves (Author) (Other); José Silva Matos (Author) (FEUP)
Definição de Requisitos para um Sistema de Validação e Teste de Cartas de Circuito Impresso com BST, relatório n.º 1 do projecto PMCT/C/TIT/937/90
José Martins Ferreira (Author) (FEUP); F. Pinto (Author) (Other); José Silva Matos (Author) (FEUP)

Educational Publication

The BST Learning Kit
José Martins Ferreira (Author) (FEUP); F. Pinto (Author) (Other); José Silva Matos (Author) (FEUP)

Article in National Scientific Journal

O Boundary Scan Test: conceitos, limitações, e perspectivas de futuro
José M. M. Ferreira (Author) (FEUP); José A. R. S. Matos (Author) (FEUP); Raul F. A. M. Vidal (Author) (FEUP); João P. C. Ferreira (Author) (FEUP); Ana M. Leão (Author) (Other)

Article in International Scientific Journal

Boundary scan test, test methodology, and fault modeling
Frans de Jong (Author) (Other); José S. Matos (Author) (FEUP); José M. Ferreira (Author) (FEUP)

Article in International Conference Proceedings Book

Um Processador para o Auto-Teste de Cartas de Circuito Impresso com BST
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Pinto (Author) (Other)
Um ASIC para o Controlo de Tempo e Temperatura em Electrodomésticos
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Pinto (Author) (Other)
O Projecto Assistido por Computador na Metodologia Boundary
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP)

Article in International Conference Proceedings Book

Board testing with boundary scan: TPG strategy
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); F. Jong (Author) (Other)
Auto-Teste de Sistemas Electrónicos com BST
José Silva Matos (Author) (FEUP); José M. M. Ferreira (Author) (FEUP); Filipe Sousa Pinto (Author) (Other)
Automatic generation of a single-chip solution for board-level BIST of boundary scan boards
José M. M. Ferreira (Author) (FEUP); Filipe S. Pinto (Author) (Other); José S. Matos (Author) (FEUP)
A new algorithm for diagnosing interconnect faults on boundary scan boards
José Martins Ferreira (Author) (FEUP); José Silva Matos (Author) (FEUP); R. Bennetts (Author) (Other); F. Jong (Author) (Other)
A modular architecture for BIST of boundary scan boards
José M. M. Ferreira (Author) (FEUP); Filipe S. Pinto (Author) (Other); José S. Matos (Author) (FEUP)

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