Go to:
Logótipo
Você está em: Start > Publications > View > The Performance Impact when Optimizing Mapping Algorithms for an FPGA-based Mobile Robot
Map of Premises
Principal
Publication

The Performance Impact when Optimizing Mapping Algorithms for an FPGA-based Mobile Robot

Title
The Performance Impact when Optimizing Mapping Algorithms for an FPGA-based Mobile Robot
Type
Article in International Conference Proceedings Book
Year
2010
Authors
Manuel Luís C. Reis
(Author)
FEUP
View Personal Page You do not have permissions to view the institutional email. Search for Participant Publications Without AUTHENTICUS Without ORCID
Conference proceedings National
Pages: 103-110
VI Jornadas sobre Sistemas Reconfiguráveis (REC'2010)
Aveiro, 4 a 5 de Fevereiro, 2010
Scientific classification
FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering
CORDIS: Technological sciences > Engineering > Electronic engineering ; Technological sciences > Engineering > Computer engineering
Other information
Resumo (PT):
Abstract (EN): FPGA-based solutions are being used to meet performance requirements in embedded systems. The mobile robotics field is an appropriate domain to evaluate whether FPGA-based systems are capable of managing complex computing tasks. This paper presents an autonomous mobile robot prototype that includes an FPGA board as the main central processing component. In this work we evaluate the prototype using mobile robotics mapping algorithms (i.e., algorithms able to build a map of the environment). These algorithms rely mainly on probabilities and are computationally intensive. The implementation used in this paper is based on an environment occupation grid. An uncertainty model of the sensor used to measure the distance of the robot to the obstacles in the environment is used to update the probabilities. We start the experiments by analysing the performance impact of using hardware modules, such as FPU and cache memory. Then, we consider modifications in the updating algorithm to reduce the overall execution time. The overall improvements allowed for an execution time of the updating task of 9.83 ms for an implementation based on Bayes’s algorithm and 10.86ms for Dempster-Shafer’s algorithm, both at the maximum distance considered.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 8
Documents
We could not find any documents associated to the publication.
Related Publications

Of the same scientific areas

Transparent Trace-Based Binary Acceleration for Reconfigurable HW/SW Systems (2013)
Article in International Scientific Journal
João Bispo; Nuno Paulino; João Cardoso; João Canas Ferreira
Run-time generation of partial FPGA configurations for subword operations (2012)
Article in International Scientific Journal
Silva, ML; João Canas Ferreira
Translating a Hash Function from Software to Hardware: A Functional Programming Approach (2012)
Article in International Conference Proceedings Book
Paulo Ferreira; João Canas Ferreira; José Carlos Alves
Real-Time Stereo Matching on FPGA (2010)
Article in International Conference Proceedings Book
Carlos Resende; João Canas Ferreira
Improving Run-Time Creation of Partial FPGA Configurations (2011)
Article in International Conference Proceedings Book
Miguel L. Silva; João Canas Ferreira

See all (15)

Recommend this page Top
Copyright 1996-2025 © Faculdade de Medicina Dentária da Universidade do Porto  I Terms and Conditions  I Acessibility  I Index A-Z  I Guest Book
Page created on: 2025-06-29 at 05:23:06 | Acceptable Use Policy | Data Protection Policy | Complaint Portal