Go to:
Esta página em português Ajuda Autenticar-se
Formação regular da Biblioteca online
You are here: Start > PDEEC0019

Site map
Edifício A (Administração) Edifício B (Aulas) - Bloco I Edifício B (Aulas) - Bloco II Edifício B (Aulas) - Bloco III Edifício B (Aulas) - Bloco IV Edifício C (Biblioteca) Edifício D (CICA) Edifício E (Química) Edifício F (Minas e Metalurgia) Edifício F (Minas e Metalurgia) Edifício G (Civil) Edifício H (Civil) Edifício I (Electrotecnia) Edifício J (Electrotecnia) Edifício K (Pavilhão FCNAUP) Edifício L (Mecânica) Edifício M (Mecânica) Edifício N (Garagem) Edifício O (Cafetaria) Edifício P (Cantina) Edifício Q (Central de Gases) Edifício R (Laboratório de Engenharia do Ambiente) Edifício S (INESC) Edifício T (Torre do INEGI) Edifício U (Nave do INEGI) Edifício X (Associação de Estudantes)

Advanced Microelectronic Systems Design

Code: PDEEC0019     Acronym: AMSD

Classification Keyword
OFICIAL Electrical and Computer Engineering

Instance: 2019/2020 - 2S

Active? Yes
Responsible unit: Department of Electrical and Computer Engineering
Course/CS Responsible: Doctoral Program in Electrical and Computer Engineering

Cycles of Study/Courses

Acronym No. of Students Study Plan Curricular Years Credits UCN Credits ECTS Contact hours Total Time
PDEEC 4 Syllabus since 2015/16 1 - 7,5 70 202,5

Teaching Staff - Responsibilities

Teacher Responsibility
José Carlos dos Santos Alves

Teaching - Hours

Recitations: 3,00
Type Teacher Classes Hour
Recitations Totals 1 3,00
João Paulo de Castro Canas Ferreira 1,50
José Carlos dos Santos Alves 1,50

Teaching language



The course is organized in 4 modules that aim to develop competences in the in microelectronics systems design, using industry-grade EDA tools. 

The first two modules address the activities of the front-end and back-end stages that comprise a complete EDA design flow. The first one is concerned with electronic system level design (ESL) methodologies for transforming algorithmic descriptions into hardware implementations, addressing the evaluation of their quality, and exploring various design tradeoffs. The second module concentrates on the back-end tasks leading to concrete physical implementations.

The other two modules address important aspects that impact all phases of the IC design and integration process. Module 3 addresses synchronization and timing issues that impact all phases of the IC design and integration process. Module 4 deals with system-level aspects of power-aware design, with emphasis on high-level modelling and estimation.

Learning outcomes and competences

At the end of this course, students with have the background needed for the design and implementation of complex integrated electronic systems, starting from high-level abstract requirements and proceeding through successive refinement stages to a complete physical implementation in a modern, highly integrated, IC technology (e.g., sub-micron CMOS or platform FPGA). Students will also acquire an understanding of the fundamental aspects of timing and quality issues involved in this task, and solid knowledge of how they influence the design decisions and methodologies.

Working method



1 – System specification and modelling:
Electronic System Level (ESL) design flows. Design modelling based on algorithmic descriptions (C/C++/SystemC). Design space exploration and system partitioning. Hardware/software co-design. Integration of IP (Intellectual Property) blocks. System and behavioural synthesis. Platform-specific design aspects.

2 – System integration and physical synthesis for cell-based ICs: Technology-driven partitioning. Floorplanning. Placement and routing. Post-layout verification.

3 – System timing and clock management: Delay models for digital circuits and interconnects. Foundations of digital circuits timing. Clocking strategies. Clock signals. Synchronization, generation and distribution. Multiple clock domains. Dynamic clock management. Timing constraints for synthesis.

4 – Power-aware system design: Modelling power consumption in digital circuits. System-level power management. Tools and methodologies for power-aware design.

Mandatory literature

Michael Fingerhoff; High-level Synthesis Blue Book. ISBN: 978-1-4500-9724-6
Scott Hauck; André DeHon; Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Morgan Kaufmann, 2007
De Micheli, Giovanni; Ernst, Rolf; Wolf, Wayne; Readings in Hardware/Software Co-Design, Morgan Kaufmann, 2002. ISBN: 9781558607026

Complementary Bibliography

Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic; Digital System Clocking:High-Performance and Low-Power Aspects, Wiley-IEEE Press, 2003. ISBN: 978-0-471-27447-6

Teaching methods and learning activities

Lectures will be used to present and discuss the course topics.
Practical work will be based on a design project that will address the main topics of the course
All support material will be available on-line.


Synopsys design compiler
MentorGraphics Catapult C
Cadence IC station


Technological sciences > Engineering > Electronic engineering
Technological sciences > Technology > Computer technology

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation Weight (%)
Exame 40,00
Trabalho prático ou de projeto 60,00
Total: 100,00

Amount of time allocated to each course unit

Designation Time (hours)
Elaboração de projeto 64,00
Estudo autónomo 112,00
Frequência das aulas 28,00
Total: 204,00

Eligibility for exams

In order to be admitted to the exams the students must have a minimum grade of 10 (out of 20) in the design project.

Calculation formula of final grade

Final grade (F) is given by:
F = 0.6 P + 0.4 E
where P is the project grade and E is the final exam grade
Recommend this page Top
Copyright 1996-2020 © Faculdade de Engenharia da Universidade do Porto  I Terms and Conditions  I Accessibility  I Index A-Z  I Guest Book
Page generated on: 2020-04-08 at 07:30:28