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Digital Systems Design

Code: EEC0055     Acronym: PSDI

Classification Keyword
OFICIAL Electronics and Digital Systems

Instance: 2018/2019 - 1S

Active? Yes
Responsible unit: Department of Electrical and Computer Engineering
Course/CS Responsible: Master in Electrical and Computers Engineering

Cycles of Study/Courses

Acronym No. of Students Study Plan Curricular Years Credits UCN Credits ECTS Contact hours Total Time
MIEEC 38 Syllabus 4 - 6 56 162
MI:EF 4 study plan from 2017/18 4 - 6 56 162

Teaching Staff - Responsibilities

Teacher Responsibility
José Carlos dos Santos Alves

Teaching - Hours

Lectures: 2,00
Laboratory Practice: 2,00
Type Teacher Classes Hour
Lectures Totals 1 2,00
José Carlos dos Santos Alves 2,00
Laboratory Practice Totals 2 4,00
Mário Lopes Ferreira 4,00

Teaching language

Suitable for English-speaking students


This course aims to endow students with technological knowledge and design methodologies to build complex custom digital systems, targeting microelectronic technologies (application specific integrated circuits - ASIC and reconfigurable digital systems - FPGA). The activity developed in the course is focused on building abstract models of digital systems using industrial hardware description languages (Verilog HDL), perform model verification by logic simulation and synthesise from RTL descriptions, exploiting a strong laboratory activity around practical projects targeting FPGA platforms.

Learning outcomes and competences

After successfully completing this course the students should be able to:

- Identify and characterize the main design tasks in the digital design flow for microelectronic technologies (ASICs and FPGAs)

- Mastering the process of coding digital systems using hardware description languages (Verilog will be used), under the perspectives of design verification and automatic synthesis.

- Planning the design verification process based on logic simulation tools and basic verification platforms.

- Design synchronous digital systems with one or more clock domains and understand the design timing constraints associated with their implementation, particularly in what concerns to the design of the clock generation and distribution networks.

- Evaluate and compare different logic implementations of basic arithmetic circuits, with respect to area and timing specifications.

- Apply design processes and methodologies to integrate pre-built blocks (intellectual property or IP), with practical application in a digital design environment for FPGAs.

- Identify the basic processes associated with the power consumption in digital microelectronic circuits (CMOS) and apply elementary design techniques to reduce the power consumption.

- Develop personal, professional and interpersonal skills (teamwork and oral and written communication) with the realization of group laboratory assignments and reports.

Working method


Pre-requirements (prior knowledge) and co-requirements (common knowledge)

Elementary background on digital sistems and Boolean algebra


Structured design flow of digital systems: design methodologies and models of representation of digital systems at different levels of abstraction; hierarchy and modularity. Hardware Description Languages (HDLs) for modelling, verification and logic synthesis. Design verification with logic simulation; functional and timing verification; elaboration of testbenches. Synthesis of digital systems at the Register Transfer Level (RTL); synthesis constraints (area and timing). Design of synchronous digital systems; issues related with the generation, management and distribution of clock signals; designs with multiple clock domains. Reconfigurable digital technologies: FPGAs and combined systems FPGA/microprocessor. Design of dedicated arithmetic datapaths: architectures of elementary arithmetic operators. Design of complex digital systems based on pre-built blocks (intelectual property or IP) Principles of low power digital design (logic, RTL and architectural levels).

Mandatory literature

Smith, Douglas J.; HDL chip design. ISBN: 0-9651934-3-8
Ciletti, Michael D.; Advanced digital design with the verilog HDL. ISBN: 0-13-089161-4

Complementary Bibliography

Bergeron, Janick; Writing testbenches. ISBN: 0-7923-7766-4
Palnitkar, Samir; Verilog HDL. ISBN: 0-13-451675-3

Teaching methods and learning activities

Theoretical classes (2 hours) will be based on the presentation of the themes of the course. Practical classes (2 hours) will be based on practical assignments to apply design methodologies, tools and concepts presented in theoretical classes. Practical assignments will be based on the use of XILINX design tools, using top-down design methodologies, based on Verilog hardware description language, automatic synthesis and implementation of reconfigurable systems based on FPGA devices. All support material will be available on line.


QuestaSim 10.4
Xilinx ISE 14.6


Physical sciences > Computer science > Digital systems
Technological sciences > Engineering > Computer engineering

Evaluation Type

Distributed evaluation with final exam

Assessment Components

Designation Weight (%)
Exame 50,00
Participação presencial 0,00
Trabalho laboratorial 50,00
Total: 100,00

Amount of time allocated to each course unit

Designation Time (hours)
Estudo autónomo 50,00
Frequência das aulas 56,00
Trabalho laboratorial 56,00
Total: 162,00

Eligibility for exams

Students have to reach a minimum mark of 40% in the practical component of the course (laboratory assignments) to be admitted to the final exam. Also, students have to follow the rules established in the General Evaluation Rules of FEUP.

Calculation formula of final grade

Final Mark will be based on the following formula (final exam 50%, laboratory assignments 50%) FM= 0,1*LA1 + 0,05*LA2 + 0,35*LA3 + 0,5*FE (LAi – Lab Assignment #i; FE – Final Exam) Students have to reach a minimum mark of 10 out of 20 to complete the course. Besides, they have to reach a minimum mark of 40% in the final exam and a minimum of 40% in the 3 laboratory assignments.

Examinations or Special Assignments

Special assignments which are done outside the regular season of assessment will be based on an exam and a practical assignment. Students with a special status, who reached a minimum mark of 40% in the practical component of the course in previous years, do not need to do it again.

Special assessment (TE, DA, ...)

Students with a special status and who cannot attend to classes, will have to do a complementary laboratory work, which is worth the same as the regular practical assignments (10 out 20).

Classification improvement

Students can improve their marks separately (exam and practical assignments). The improvement of the pratical assignments can be done in the next year.


Classes will be given in Portuguese. However, if there are foreign students who do not understand Portuguese, special classes will be organized in English for them.

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