Real-Time Stereo Matching on FPGA

• Type: Article in International Conference Proceedings Book
• Date: 2010

Authors

Carlos Resende (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings National

Title: Actas das VI Jornadas sobre Sistemas Reconfiguráveis - REC'2010

Pages: 129-136

VI Jornadas sobre Sistemas Reconfiguráveis (REC'2010)

Aveiro, 4 a 5 de Fevereiro, 2010

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electronic engineering ; Technological sciences > Engineering > Computer engineering

Other information

Abstract (EN): Real-time stereo image matching is an important computer vision task, with applications in robotics, driver assistance, surveillance and other domains. The paper describes the architecture and implementation of an FPGA-based stereo image processor that can produce 25 dense depth maps per second from pairs of 8-bit grayscale images. The system uses a modification of a previously-reported variable-window-size method to determine the best match for each image pixel. The adaptation is empirically shown to have negligible impact on the quality of the resulting depth map. The degree of parallelism of the implementation can be adapted to the available resources: increased parallelism enables the processing of larger images at the same frame rate (40ms per image). The architecture exploits the memory resources available in modern platform FPGAs. Two prototype implementations have been produced and validated. The smaller one can handle pairs of images of size 208x480 (on a Virtex-4 LX60 at 100MHz); the larger one works for images of size 640x480 (on a Virtex-5 LX330 at 100MHz). These results improve on previously-reported ASIC and FPGA-based designs.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 9