LALP: A Language to Program Custom FPGA-Based Acceleration Engines

• Type: Article in International Scientific Journal
• Date: 2012

Authors

Menotti, R (Author) Other; João M. P. Cardoso (Author) FEUP; Fernandes, MM (Author) Other; Marques, E (Author) Other

Journal

Title: International Journal of Parallel Programming

Vol. 40

Pages: 262-289

ISSN: 0885-7458

Publisher: Springer Nature

Indexing

ISI Web of Knowledge - 6 Citations

Scopus - 6 Citations

Other information

Authenticus ID: P-002-9WH

DOI: 10.1007/s10766-011-0187-0

Abstract (EN): Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 28