Go to:
Logótipo
Comuta visibilidade da coluna esquerda
Você está em: Start > Publications > View > A Lock-Free Hash Trie Design for Concurrent Tabled Logic Programs
Publication

A Lock-Free Hash Trie Design for Concurrent Tabled Logic Programs

Title
A Lock-Free Hash Trie Design for Concurrent Tabled Logic Programs
Type
Article in International Scientific Journal
Year
2016
Authors
Miguel Areias
(Author)
FCUP
View Personal Page You do not have permissions to view the institutional email. Search for Participant Publications View Authenticus page View ORCID page
Ricardo Rocha
(Author)
FCUP
View Personal Page You do not have permissions to view the institutional email. Search for Participant Publications View Authenticus page View ORCID page
Journal
Vol. 44
Pages: 386-406
ISSN: 0885-7458
Publisher: Springer Nature
Other information
Authenticus ID: P-00F-YAG
Abstract (EN): Tabling is an implementation technique that improves the declarativeness and expressiveness of Prolog systems in dealing with recursion and redundant sub-computations. A critical component in the design of a concurrent tabling system is the implementation of the table space. One of the most successful proposals for representing tables is based on a two-level trie data structure, where one trie level stores the tabled subgoal calls and the other stores the computed answers. In previous work, we have presented a sophisticated lock-free design where both levels of the tries where shared among threads in a concurrent environment. To implement lock-freedom we used the CAS atomic instruction that nowadays is widely found on many common architectures. CAS reduces the granularity of the synchronization when threads access concurrent areas, but still suffers from problems such as false sharing or cache memory effects. In this work, we present a simpler and efficient lock-free design based on hash tries that minimizes these problems by dispersing the concurrent areas as much as possible. Experimental results in the Yap Prolog system show that our new lock-free design can effectively reduce the execution time and scales better than previous designs.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 21
Documents
We could not find any documents associated to the publication.
Related Publications

Of the same authors

On Applying Linear Tabling to Logic Programs (2010)
Thesis
MIGUEL AREIAS; Ricardo Rocha
Towards multi-threaded local tabling using a common table space (2012)
Article in International Scientific Journal
Miguel Areias; Ricardo Rocha
Table space designs for implicit and explicit concurrent tabled evaluation (2018)
Article in International Scientific Journal
Miguel Areias; Ricardo Rocha
On the implementation of memory reclamation methods in a lock-free hash trie design (2021)
Article in International Scientific Journal
Moreno, P; Miguel Areias; Ricardo Rocha

See all (28)

Of the same journal

Special Issue on High-Level Parallel Programming and Applications (2022)
Another Publication in an International Scientific Journal
Jorge Manuel Gomes Barbosa; Ines Dutra; Miguel Areias
Relational Learning with GPUs: Accelerating Rule Coverage (2016)
Article in International Scientific Journal
Alberto Martinez Angeles, CA; Wu, HC; Ines Dutra; Costa, VS; Buenabad Chavez, J
Parallel Asynchronous Strategies for the Execution of Feature Selection Algorithms (2018)
Article in International Scientific Journal
Jorge Silva; Ana Aguiar; Fernando Silva
LALP: A Language to Program Custom FPGA-Based Acceleration Engines (2012)
Article in International Scientific Journal
Menotti, R; João M. P. Cardoso; Fernandes, MM; Marques, E
Recommend this page Top
Copyright 1996-2024 © Faculdade de Economia da Universidade do Porto  I Terms and Conditions  I Acessibility  I Index A-Z  I Guest Book
Page created on: 2024-10-28 at 16:23:40 | Acceptable Use Policy | Data Protection Policy | Complaint Portal
SAMA2