From circuit simulation to circuit verification: an internal+boundary-scan-based solution

• Tipo: Artigo em Livro de Atas de Conferência Internacional
• Data: 2000

Autores

Gustavo Costa Alves (Autor) Outra; Marcelo Lubaszewski (Autor) Outra; Margrit Krug (Autor) Outra; José Martins Ferreira (Autor) FEUP

Ata de Conferência Internacional

Título: Proceedings of the European Test Workshop ETW'00

Páginas: 1-3

European Test Workshop ETW¿00

Cascais, Portugal, 23 a 26 de Maio de 2000

Classificação Científica

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

Abstract (EN): Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program encompasses the design and development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 3