The influence of architectural parameters on the performance of parallel logic programming systems

• Type: Article in International Scientific Journal
• Date: 1999

Authors

Silva, MG (Author) Other; Dutra, IC (Author) Other; Bianchini, R (Author) Other; Costa, VS (Author) FCUP

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 4 Citations

Scientific classification

FOS: Natural sciences > Computer and information sciences

Other information

Authenticus ID: P-001-65B

DOI: 10.1007/3-540-49201-1_9

Abstract (EN): In this work we investigate how different machine settings for a hardware Distributed Shared Memory (DSM) architecture affect the performance of parallel logic programming (PLP) systems. We use execution-driven simulation of a DASH-like multiprocessor to study the impact of the cache block size, the cache size, the network bandwidth, the write buffer size, and the coherence protocol on the performance of Andorra-I, a PLP system capable of exploiting implicit parallelism in Prolog programs. Among several other observations, we find that PLP systems favour small cache blocks regardless of the coherence protocol, while they favour large cache sizes only in the case of invalidate-based coherence. We conclude that the cache block size, the cache size, the network bandwidth, and the coherence protocol have a significant impact on the performance, while the size of the write buffer is somewhat irrelevant.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 15