Thermal and residual stresses at the EMC-silicon interface: From wafer manufacturing to fracture test

• Type: Article in International Scientific Journal
• Date: 2025

Authors

Videira, PFC (Author) Other; Akhavan-Safar, A (Author) Other; Maleki, P (Author) Other; Carbas, RJC (Author) Other; Marques, EAS (Author) Other; Karunamurthy, B (Author) Other; da Silva, LFM (Author) FEUP

Journal

Title: Materials Today Communications

Vol. 45

ISSN: 2352-4928

Publisher: Elsevier

Indexing

ISI Web of Knowledge - 0 Citations

Scopus - 0 Citations

Other information

Authenticus ID: P-018-BD5

DOI: 10.1016/j.mtcomm.2025.112218

Abstract (EN): A comprehensive understanding of the manufacturing and testing of wafer assemblies, as well as the monitoring of induced stresses during these processes, contributes to the reliability and performance of microelectronic devices. Despite numerous studies on the general impact of thermal stresses, the evolution of thermal and residual stresses at the interface of epoxy molding compound (EMC)-silicon in microelectronic assemblies has not been addressed. This study addresses this gap by proposing an innovative approach combining analytical, numerical, and experimental methods to investigate the evolution of thermal and residual stresses at the EMCsilicon interface in microprocessors. The work considers three sequential stages: wafer manufacturing, double cantilever beam (DCB) joint assembly, and fracture testing under varied temperatures (-20 degrees C, 20 degrees C, and 100 degrees C). Experimental fracture tests revealed a marked temperature dependency in interfacial fracture behavior. The critical strain energy release rates (GIC) were found to be 0.05 N/mm at room temperature (20 degrees C), 0.13 N/mm at -20 degrees C, and 0.37 N/mm at 100 degrees C. FE analyses further demonstrated that, at room temperature, the maximum stresses reached approximately 19 % and 25 % of the ultimate tensile strength (UTS) in the silicon and EMC layers, respectively. In contrast, at 100 degrees C, the silicon layer experienced stresses slightly exceeding its ultimate tensile strength (UTS) by 1 %, while at -20 degrees C, the silicon and EMC layers sustained stress levels of about 55 % and 36 % of their UTS, respectively. These quantitative findings highlight that fracture energy obtained from a DCB test should be interpreted by considering the thermal history that the sample has experienced before and during the test. The distribution of thermal residual stresses from wafer fabrication and the impact of sample preparation for testing on residual stresses, as well as how testing at different temperatures alters these stresses, are crucial. These stresses can explain some of the variations in fracture energy, and these results are particularly important for designing microchips that experience diverse manufacturing and operating temperatures, ensuring the safe design of these components.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 11